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Description: asynchronous fifo with pulse input
write by verilog code
Platform: |
Size: 2048 |
Author: Long |
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Description: 基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit，深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
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Size: 677888 |
Author: 杨杨 |
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Description: FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
Platform: |
Size: 3072 |
Author: andThe |
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Description: verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
Platform: |
Size: 2048 |
Author: dropins |
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Description: verilog代码写的控制vga显示的实例，利用状态机进行描述，很好的参考例子-verilog language write serial fifo instance, because the serial port speed is relatively slow, a lot of the interface will use fifo buffer
Platform: |
Size: 100352 |
Author: 崔帅 |
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Description: 本代码提供一种音频I2S读取数据的verilog代码，并且向fifo写入-This code provides an I2S audio data is read verilog code, and write to the fifo
Platform: |
Size: 1024 |
Author: Wang Xue |
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Description: 异步fifo 先进先出 用于缓冲数据，用verilog HDL所写，在quartus II中测试通过，modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
Platform: |
Size: 4096 |
Author: T~T |
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Description:
本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by port can be divided into TPRAM, DPRAM, TPRAM read one each port, a port read-only, write-only another port, DPRAM read each one each port, each port can either be read. This article synchronous FIFO is TPRAM (two-port RAM, a read a write).
Platform: |
Size: 650240 |
Author: jodyql |
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Description: FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
Platform: |
Size: 3072 |
Author: eofper |
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Description: verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
Platform: |
Size: 2048 |
Author: WhieHou |
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Description: 本人自己经过实践检验的SRAM读写器，用Verilog编写的，可以作为FIFO使用。-I own proven SRAM reader, using Verilog prepared, can be used as a FIFO.
Platform: |
Size: 1024 |
Author: 孟德 |
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Description: 这个是最新的UART的verilog代码，里边含有和UART相关的所有function,比如状态机，接收发送FIFO等相关代码。-New UART verilog sample code,Include FIFO code state mashine code ,recevier/trasmiter code
Platform: |
Size: 4096 |
Author: parkershe |
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Description: (1)FT245BL芯片datasheet(2)test，USB 转FIFO 芯片测试的verilog程序-(1) FT245BL chip datasheet (2) test, USB transfer FIFO chip testing procedures verilog
Platform: |
Size: 427008 |
Author: wangqiang |
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Description: verilog实现的，异步FIFO。所有代码在一个模块中。-verilog achieve, asynchronous FIFO. All code in a module.
Platform: |
Size: 1024 |
Author: 刘禹韬 |
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Description: 由verilog实现的，异步FIFO，分为多模块实现。-Verilog achieved by the asynchronous FIFO, divided into multiple modules.
Platform: |
Size: 1024 |
Author: 刘禹韬 |
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Description: VERILOG AD采集程序 FIFO存储-VERILOG AD acquisition program FIFO memory
Platform: |
Size: 739328 |
Author: |
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Description: 基于FPGA设计，verilog语言变成的，SPI通用接口模块，顶层已封装成类似标准的FIFO接口；提供仿真文件；仿真器为modelsim10.0c，波形观察debussy。-Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface similar to that of the standard provide simulation files simulator for modelsim10.0c, waveform observation debussy.
Platform: |
Size: 553984 |
Author: Zou Xingyu |
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Description: SYNCHRONOUS FIFO EXAMPLE IN VERILOG
Platform: |
Size: 1024 |
Author: Nik |
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Description: 16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
Platform: |
Size: 33792 |
Author: chenhaoc |
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Description: verilog asyn_fifo,内含详细说明,同步FIFO为TPRAM-asyn_fifo include detailed instruction，Synchronous FIFO for TPRAM
Platform: |
Size: 389120 |
Author: 杨莉莉 |
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